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-rw-r--r--vendor/golang.org/x/sys/cpu/asm_aix_ppc64.s17
-rw-r--r--vendor/golang.org/x/sys/cpu/byteorder.go66
-rw-r--r--vendor/golang.org/x/sys/cpu/cpu.go290
-rw-r--r--vendor/golang.org/x/sys/cpu/cpu_aix.go33
-rw-r--r--vendor/golang.org/x/sys/cpu/cpu_arm.go73
-rw-r--r--vendor/golang.org/x/sys/cpu/cpu_arm64.go172
-rw-r--r--vendor/golang.org/x/sys/cpu/cpu_arm64.s31
-rw-r--r--vendor/golang.org/x/sys/cpu/cpu_gc_arm64.go11
-rw-r--r--vendor/golang.org/x/sys/cpu/cpu_gc_s390x.go21
-rw-r--r--vendor/golang.org/x/sys/cpu/cpu_gc_x86.go15
-rw-r--r--vendor/golang.org/x/sys/cpu/cpu_gccgo_arm64.go11
-rw-r--r--vendor/golang.org/x/sys/cpu/cpu_gccgo_s390x.go22
-rw-r--r--vendor/golang.org/x/sys/cpu/cpu_gccgo_x86.c37
-rw-r--r--vendor/golang.org/x/sys/cpu/cpu_gccgo_x86.go31
-rw-r--r--vendor/golang.org/x/sys/cpu/cpu_linux.go15
-rw-r--r--vendor/golang.org/x/sys/cpu/cpu_linux_arm.go39
-rw-r--r--vendor/golang.org/x/sys/cpu/cpu_linux_arm64.go111
-rw-r--r--vendor/golang.org/x/sys/cpu/cpu_linux_mips64x.go22
-rw-r--r--vendor/golang.org/x/sys/cpu/cpu_linux_noinit.go9
-rw-r--r--vendor/golang.org/x/sys/cpu/cpu_linux_ppc64x.go30
-rw-r--r--vendor/golang.org/x/sys/cpu/cpu_linux_s390x.go40
-rw-r--r--vendor/golang.org/x/sys/cpu/cpu_loong64.go12
-rw-r--r--vendor/golang.org/x/sys/cpu/cpu_mips64x.go15
-rw-r--r--vendor/golang.org/x/sys/cpu/cpu_mipsx.go11
-rw-r--r--vendor/golang.org/x/sys/cpu/cpu_netbsd_arm64.go173
-rw-r--r--vendor/golang.org/x/sys/cpu/cpu_openbsd_arm64.go65
-rw-r--r--vendor/golang.org/x/sys/cpu/cpu_openbsd_arm64.s11
-rw-r--r--vendor/golang.org/x/sys/cpu/cpu_other_arm.go9
-rw-r--r--vendor/golang.org/x/sys/cpu/cpu_other_arm64.go9
-rw-r--r--vendor/golang.org/x/sys/cpu/cpu_other_mips64x.go11
-rw-r--r--vendor/golang.org/x/sys/cpu/cpu_other_ppc64x.go12
-rw-r--r--vendor/golang.org/x/sys/cpu/cpu_other_riscv64.go11
-rw-r--r--vendor/golang.org/x/sys/cpu/cpu_ppc64x.go16
-rw-r--r--vendor/golang.org/x/sys/cpu/cpu_riscv64.go11
-rw-r--r--vendor/golang.org/x/sys/cpu/cpu_s390x.go172
-rw-r--r--vendor/golang.org/x/sys/cpu/cpu_s390x.s57
-rw-r--r--vendor/golang.org/x/sys/cpu/cpu_wasm.go17
-rw-r--r--vendor/golang.org/x/sys/cpu/cpu_x86.go151
-rw-r--r--vendor/golang.org/x/sys/cpu/cpu_x86.s26
-rw-r--r--vendor/golang.org/x/sys/cpu/cpu_zos.go10
-rw-r--r--vendor/golang.org/x/sys/cpu/cpu_zos_s390x.go25
-rw-r--r--vendor/golang.org/x/sys/cpu/endian_big.go10
-rw-r--r--vendor/golang.org/x/sys/cpu/endian_little.go10
-rw-r--r--vendor/golang.org/x/sys/cpu/hwcap_linux.go71
-rw-r--r--vendor/golang.org/x/sys/cpu/parse.go43
-rw-r--r--vendor/golang.org/x/sys/cpu/proc_cpuinfo_linux.go53
-rw-r--r--vendor/golang.org/x/sys/cpu/runtime_auxv.go16
-rw-r--r--vendor/golang.org/x/sys/cpu/runtime_auxv_go121.go18
-rw-r--r--vendor/golang.org/x/sys/cpu/syscall_aix_gccgo.go26
-rw-r--r--vendor/golang.org/x/sys/cpu/syscall_aix_ppc64_gc.go35
50 files changed, 2202 insertions, 0 deletions
diff --git a/vendor/golang.org/x/sys/cpu/asm_aix_ppc64.s b/vendor/golang.org/x/sys/cpu/asm_aix_ppc64.s
new file mode 100644
index 0000000..269e173
--- /dev/null
+++ b/vendor/golang.org/x/sys/cpu/asm_aix_ppc64.s
@@ -0,0 +1,17 @@
1// Copyright 2018 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5//go:build gc
6
7#include "textflag.h"
8
9//
10// System calls for ppc64, AIX are implemented in runtime/syscall_aix.go
11//
12
13TEXT ·syscall6(SB),NOSPLIT,$0-88
14 JMP syscall·syscall6(SB)
15
16TEXT ·rawSyscall6(SB),NOSPLIT,$0-88
17 JMP syscall·rawSyscall6(SB)
diff --git a/vendor/golang.org/x/sys/cpu/byteorder.go b/vendor/golang.org/x/sys/cpu/byteorder.go
new file mode 100644
index 0000000..271055b
--- /dev/null
+++ b/vendor/golang.org/x/sys/cpu/byteorder.go
@@ -0,0 +1,66 @@
1// Copyright 2019 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5package cpu
6
7import (
8 "runtime"
9)
10
11// byteOrder is a subset of encoding/binary.ByteOrder.
12type byteOrder interface {
13 Uint32([]byte) uint32
14 Uint64([]byte) uint64
15}
16
17type littleEndian struct{}
18type bigEndian struct{}
19
20func (littleEndian) Uint32(b []byte) uint32 {
21 _ = b[3] // bounds check hint to compiler; see golang.org/issue/14808
22 return uint32(b[0]) | uint32(b[1])<<8 | uint32(b[2])<<16 | uint32(b[3])<<24
23}
24
25func (littleEndian) Uint64(b []byte) uint64 {
26 _ = b[7] // bounds check hint to compiler; see golang.org/issue/14808
27 return uint64(b[0]) | uint64(b[1])<<8 | uint64(b[2])<<16 | uint64(b[3])<<24 |
28 uint64(b[4])<<32 | uint64(b[5])<<40 | uint64(b[6])<<48 | uint64(b[7])<<56
29}
30
31func (bigEndian) Uint32(b []byte) uint32 {
32 _ = b[3] // bounds check hint to compiler; see golang.org/issue/14808
33 return uint32(b[3]) | uint32(b[2])<<8 | uint32(b[1])<<16 | uint32(b[0])<<24
34}
35
36func (bigEndian) Uint64(b []byte) uint64 {
37 _ = b[7] // bounds check hint to compiler; see golang.org/issue/14808
38 return uint64(b[7]) | uint64(b[6])<<8 | uint64(b[5])<<16 | uint64(b[4])<<24 |
39 uint64(b[3])<<32 | uint64(b[2])<<40 | uint64(b[1])<<48 | uint64(b[0])<<56
40}
41
42// hostByteOrder returns littleEndian on little-endian machines and
43// bigEndian on big-endian machines.
44func hostByteOrder() byteOrder {
45 switch runtime.GOARCH {
46 case "386", "amd64", "amd64p32",
47 "alpha",
48 "arm", "arm64",
49 "loong64",
50 "mipsle", "mips64le", "mips64p32le",
51 "nios2",
52 "ppc64le",
53 "riscv", "riscv64",
54 "sh":
55 return littleEndian{}
56 case "armbe", "arm64be",
57 "m68k",
58 "mips", "mips64", "mips64p32",
59 "ppc", "ppc64",
60 "s390", "s390x",
61 "shbe",
62 "sparc", "sparc64":
63 return bigEndian{}
64 }
65 panic("unknown architecture")
66}
diff --git a/vendor/golang.org/x/sys/cpu/cpu.go b/vendor/golang.org/x/sys/cpu/cpu.go
new file mode 100644
index 0000000..4756ad5
--- /dev/null
+++ b/vendor/golang.org/x/sys/cpu/cpu.go
@@ -0,0 +1,290 @@
1// Copyright 2018 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5// Package cpu implements processor feature detection for
6// various CPU architectures.
7package cpu
8
9import (
10 "os"
11 "strings"
12)
13
14// Initialized reports whether the CPU features were initialized.
15//
16// For some GOOS/GOARCH combinations initialization of the CPU features depends
17// on reading an operating specific file, e.g. /proc/self/auxv on linux/arm
18// Initialized will report false if reading the file fails.
19var Initialized bool
20
21// CacheLinePad is used to pad structs to avoid false sharing.
22type CacheLinePad struct{ _ [cacheLineSize]byte }
23
24// X86 contains the supported CPU features of the
25// current X86/AMD64 platform. If the current platform
26// is not X86/AMD64 then all feature flags are false.
27//
28// X86 is padded to avoid false sharing. Further the HasAVX
29// and HasAVX2 are only set if the OS supports XMM and YMM
30// registers in addition to the CPUID feature bit being set.
31var X86 struct {
32 _ CacheLinePad
33 HasAES bool // AES hardware implementation (AES NI)
34 HasADX bool // Multi-precision add-carry instruction extensions
35 HasAVX bool // Advanced vector extension
36 HasAVX2 bool // Advanced vector extension 2
37 HasAVX512 bool // Advanced vector extension 512
38 HasAVX512F bool // Advanced vector extension 512 Foundation Instructions
39 HasAVX512CD bool // Advanced vector extension 512 Conflict Detection Instructions
40 HasAVX512ER bool // Advanced vector extension 512 Exponential and Reciprocal Instructions
41 HasAVX512PF bool // Advanced vector extension 512 Prefetch Instructions
42 HasAVX512VL bool // Advanced vector extension 512 Vector Length Extensions
43 HasAVX512BW bool // Advanced vector extension 512 Byte and Word Instructions
44 HasAVX512DQ bool // Advanced vector extension 512 Doubleword and Quadword Instructions
45 HasAVX512IFMA bool // Advanced vector extension 512 Integer Fused Multiply Add
46 HasAVX512VBMI bool // Advanced vector extension 512 Vector Byte Manipulation Instructions
47 HasAVX5124VNNIW bool // Advanced vector extension 512 Vector Neural Network Instructions Word variable precision
48 HasAVX5124FMAPS bool // Advanced vector extension 512 Fused Multiply Accumulation Packed Single precision
49 HasAVX512VPOPCNTDQ bool // Advanced vector extension 512 Double and quad word population count instructions
50 HasAVX512VPCLMULQDQ bool // Advanced vector extension 512 Vector carry-less multiply operations
51 HasAVX512VNNI bool // Advanced vector extension 512 Vector Neural Network Instructions
52 HasAVX512GFNI bool // Advanced vector extension 512 Galois field New Instructions
53 HasAVX512VAES bool // Advanced vector extension 512 Vector AES instructions
54 HasAVX512VBMI2 bool // Advanced vector extension 512 Vector Byte Manipulation Instructions 2
55 HasAVX512BITALG bool // Advanced vector extension 512 Bit Algorithms
56 HasAVX512BF16 bool // Advanced vector extension 512 BFloat16 Instructions
57 HasAMXTile bool // Advanced Matrix Extension Tile instructions
58 HasAMXInt8 bool // Advanced Matrix Extension Int8 instructions
59 HasAMXBF16 bool // Advanced Matrix Extension BFloat16 instructions
60 HasBMI1 bool // Bit manipulation instruction set 1
61 HasBMI2 bool // Bit manipulation instruction set 2
62 HasCX16 bool // Compare and exchange 16 Bytes
63 HasERMS bool // Enhanced REP for MOVSB and STOSB
64 HasFMA bool // Fused-multiply-add instructions
65 HasOSXSAVE bool // OS supports XSAVE/XRESTOR for saving/restoring XMM registers.
66 HasPCLMULQDQ bool // PCLMULQDQ instruction - most often used for AES-GCM
67 HasPOPCNT bool // Hamming weight instruction POPCNT.
68 HasRDRAND bool // RDRAND instruction (on-chip random number generator)
69 HasRDSEED bool // RDSEED instruction (on-chip random number generator)
70 HasSSE2 bool // Streaming SIMD extension 2 (always available on amd64)
71 HasSSE3 bool // Streaming SIMD extension 3
72 HasSSSE3 bool // Supplemental streaming SIMD extension 3
73 HasSSE41 bool // Streaming SIMD extension 4 and 4.1
74 HasSSE42 bool // Streaming SIMD extension 4 and 4.2
75 _ CacheLinePad
76}
77
78// ARM64 contains the supported CPU features of the
79// current ARMv8(aarch64) platform. If the current platform
80// is not arm64 then all feature flags are false.
81var ARM64 struct {
82 _ CacheLinePad
83 HasFP bool // Floating-point instruction set (always available)
84 HasASIMD bool // Advanced SIMD (always available)
85 HasEVTSTRM bool // Event stream support
86 HasAES bool // AES hardware implementation
87 HasPMULL bool // Polynomial multiplication instruction set
88 HasSHA1 bool // SHA1 hardware implementation
89 HasSHA2 bool // SHA2 hardware implementation
90 HasCRC32 bool // CRC32 hardware implementation
91 HasATOMICS bool // Atomic memory operation instruction set
92 HasFPHP bool // Half precision floating-point instruction set
93 HasASIMDHP bool // Advanced SIMD half precision instruction set
94 HasCPUID bool // CPUID identification scheme registers
95 HasASIMDRDM bool // Rounding double multiply add/subtract instruction set
96 HasJSCVT bool // Javascript conversion from floating-point to integer
97 HasFCMA bool // Floating-point multiplication and addition of complex numbers
98 HasLRCPC bool // Release Consistent processor consistent support
99 HasDCPOP bool // Persistent memory support
100 HasSHA3 bool // SHA3 hardware implementation
101 HasSM3 bool // SM3 hardware implementation
102 HasSM4 bool // SM4 hardware implementation
103 HasASIMDDP bool // Advanced SIMD double precision instruction set
104 HasSHA512 bool // SHA512 hardware implementation
105 HasSVE bool // Scalable Vector Extensions
106 HasASIMDFHM bool // Advanced SIMD multiplication FP16 to FP32
107 _ CacheLinePad
108}
109
110// ARM contains the supported CPU features of the current ARM (32-bit) platform.
111// All feature flags are false if:
112// 1. the current platform is not arm, or
113// 2. the current operating system is not Linux.
114var ARM struct {
115 _ CacheLinePad
116 HasSWP bool // SWP instruction support
117 HasHALF bool // Half-word load and store support
118 HasTHUMB bool // ARM Thumb instruction set
119 Has26BIT bool // Address space limited to 26-bits
120 HasFASTMUL bool // 32-bit operand, 64-bit result multiplication support
121 HasFPA bool // Floating point arithmetic support
122 HasVFP bool // Vector floating point support
123 HasEDSP bool // DSP Extensions support
124 HasJAVA bool // Java instruction set
125 HasIWMMXT bool // Intel Wireless MMX technology support
126 HasCRUNCH bool // MaverickCrunch context switching and handling
127 HasTHUMBEE bool // Thumb EE instruction set
128 HasNEON bool // NEON instruction set
129 HasVFPv3 bool // Vector floating point version 3 support
130 HasVFPv3D16 bool // Vector floating point version 3 D8-D15
131 HasTLS bool // Thread local storage support
132 HasVFPv4 bool // Vector floating point version 4 support
133 HasIDIVA bool // Integer divide instruction support in ARM mode
134 HasIDIVT bool // Integer divide instruction support in Thumb mode
135 HasVFPD32 bool // Vector floating point version 3 D15-D31
136 HasLPAE bool // Large Physical Address Extensions
137 HasEVTSTRM bool // Event stream support
138 HasAES bool // AES hardware implementation
139 HasPMULL bool // Polynomial multiplication instruction set
140 HasSHA1 bool // SHA1 hardware implementation
141 HasSHA2 bool // SHA2 hardware implementation
142 HasCRC32 bool // CRC32 hardware implementation
143 _ CacheLinePad
144}
145
146// MIPS64X contains the supported CPU features of the current mips64/mips64le
147// platforms. If the current platform is not mips64/mips64le or the current
148// operating system is not Linux then all feature flags are false.
149var MIPS64X struct {
150 _ CacheLinePad
151 HasMSA bool // MIPS SIMD architecture
152 _ CacheLinePad
153}
154
155// PPC64 contains the supported CPU features of the current ppc64/ppc64le platforms.
156// If the current platform is not ppc64/ppc64le then all feature flags are false.
157//
158// For ppc64/ppc64le, it is safe to check only for ISA level starting on ISA v3.00,
159// since there are no optional categories. There are some exceptions that also
160// require kernel support to work (DARN, SCV), so there are feature bits for
161// those as well. The struct is padded to avoid false sharing.
162var PPC64 struct {
163 _ CacheLinePad
164 HasDARN bool // Hardware random number generator (requires kernel enablement)
165 HasSCV bool // Syscall vectored (requires kernel enablement)
166 IsPOWER8 bool // ISA v2.07 (POWER8)
167 IsPOWER9 bool // ISA v3.00 (POWER9), implies IsPOWER8
168 _ CacheLinePad
169}
170
171// S390X contains the supported CPU features of the current IBM Z
172// (s390x) platform. If the current platform is not IBM Z then all
173// feature flags are false.
174//
175// S390X is padded to avoid false sharing. Further HasVX is only set
176// if the OS supports vector registers in addition to the STFLE
177// feature bit being set.
178var S390X struct {
179 _ CacheLinePad
180 HasZARCH bool // z/Architecture mode is active [mandatory]
181 HasSTFLE bool // store facility list extended
182 HasLDISP bool // long (20-bit) displacements
183 HasEIMM bool // 32-bit immediates
184 HasDFP bool // decimal floating point
185 HasETF3EH bool // ETF-3 enhanced
186 HasMSA bool // message security assist (CPACF)
187 HasAES bool // KM-AES{128,192,256} functions
188 HasAESCBC bool // KMC-AES{128,192,256} functions
189 HasAESCTR bool // KMCTR-AES{128,192,256} functions
190 HasAESGCM bool // KMA-GCM-AES{128,192,256} functions
191 HasGHASH bool // KIMD-GHASH function
192 HasSHA1 bool // K{I,L}MD-SHA-1 functions
193 HasSHA256 bool // K{I,L}MD-SHA-256 functions
194 HasSHA512 bool // K{I,L}MD-SHA-512 functions
195 HasSHA3 bool // K{I,L}MD-SHA3-{224,256,384,512} and K{I,L}MD-SHAKE-{128,256} functions
196 HasVX bool // vector facility
197 HasVXE bool // vector-enhancements facility 1
198 _ CacheLinePad
199}
200
201func init() {
202 archInit()
203 initOptions()
204 processOptions()
205}
206
207// options contains the cpu debug options that can be used in GODEBUG.
208// Options are arch dependent and are added by the arch specific initOptions functions.
209// Features that are mandatory for the specific GOARCH should have the Required field set
210// (e.g. SSE2 on amd64).
211var options []option
212
213// Option names should be lower case. e.g. avx instead of AVX.
214type option struct {
215 Name string
216 Feature *bool
217 Specified bool // whether feature value was specified in GODEBUG
218 Enable bool // whether feature should be enabled
219 Required bool // whether feature is mandatory and can not be disabled
220}
221
222func processOptions() {
223 env := os.Getenv("GODEBUG")
224field:
225 for env != "" {
226 field := ""
227 i := strings.IndexByte(env, ',')
228 if i < 0 {
229 field, env = env, ""
230 } else {
231 field, env = env[:i], env[i+1:]
232 }
233 if len(field) < 4 || field[:4] != "cpu." {
234 continue
235 }
236 i = strings.IndexByte(field, '=')
237 if i < 0 {
238 print("GODEBUG sys/cpu: no value specified for \"", field, "\"\n")
239 continue
240 }
241 key, value := field[4:i], field[i+1:] // e.g. "SSE2", "on"
242
243 var enable bool
244 switch value {
245 case "on":
246 enable = true
247 case "off":
248 enable = false
249 default:
250 print("GODEBUG sys/cpu: value \"", value, "\" not supported for cpu option \"", key, "\"\n")
251 continue field
252 }
253
254 if key == "all" {
255 for i := range options {
256 options[i].Specified = true
257 options[i].Enable = enable || options[i].Required
258 }
259 continue field
260 }
261
262 for i := range options {
263 if options[i].Name == key {
264 options[i].Specified = true
265 options[i].Enable = enable
266 continue field
267 }
268 }
269
270 print("GODEBUG sys/cpu: unknown cpu feature \"", key, "\"\n")
271 }
272
273 for _, o := range options {
274 if !o.Specified {
275 continue
276 }
277
278 if o.Enable && !*o.Feature {
279 print("GODEBUG sys/cpu: can not enable \"", o.Name, "\", missing CPU support\n")
280 continue
281 }
282
283 if !o.Enable && o.Required {
284 print("GODEBUG sys/cpu: can not disable \"", o.Name, "\", required CPU feature\n")
285 continue
286 }
287
288 *o.Feature = o.Enable
289 }
290}
diff --git a/vendor/golang.org/x/sys/cpu/cpu_aix.go b/vendor/golang.org/x/sys/cpu/cpu_aix.go
new file mode 100644
index 0000000..9bf0c32
--- /dev/null
+++ b/vendor/golang.org/x/sys/cpu/cpu_aix.go
@@ -0,0 +1,33 @@
1// Copyright 2019 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5//go:build aix
6
7package cpu
8
9const (
10 // getsystemcfg constants
11 _SC_IMPL = 2
12 _IMPL_POWER8 = 0x10000
13 _IMPL_POWER9 = 0x20000
14)
15
16func archInit() {
17 impl := getsystemcfg(_SC_IMPL)
18 if impl&_IMPL_POWER8 != 0 {
19 PPC64.IsPOWER8 = true
20 }
21 if impl&_IMPL_POWER9 != 0 {
22 PPC64.IsPOWER8 = true
23 PPC64.IsPOWER9 = true
24 }
25
26 Initialized = true
27}
28
29func getsystemcfg(label int) (n uint64) {
30 r0, _ := callgetsystemcfg(label)
31 n = uint64(r0)
32 return
33}
diff --git a/vendor/golang.org/x/sys/cpu/cpu_arm.go b/vendor/golang.org/x/sys/cpu/cpu_arm.go
new file mode 100644
index 0000000..301b752
--- /dev/null
+++ b/vendor/golang.org/x/sys/cpu/cpu_arm.go
@@ -0,0 +1,73 @@
1// Copyright 2018 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5package cpu
6
7const cacheLineSize = 32
8
9// HWCAP/HWCAP2 bits.
10// These are specific to Linux.
11const (
12 hwcap_SWP = 1 << 0
13 hwcap_HALF = 1 << 1
14 hwcap_THUMB = 1 << 2
15 hwcap_26BIT = 1 << 3
16 hwcap_FAST_MULT = 1 << 4
17 hwcap_FPA = 1 << 5
18 hwcap_VFP = 1 << 6
19 hwcap_EDSP = 1 << 7
20 hwcap_JAVA = 1 << 8
21 hwcap_IWMMXT = 1 << 9
22 hwcap_CRUNCH = 1 << 10
23 hwcap_THUMBEE = 1 << 11
24 hwcap_NEON = 1 << 12
25 hwcap_VFPv3 = 1 << 13
26 hwcap_VFPv3D16 = 1 << 14
27 hwcap_TLS = 1 << 15
28 hwcap_VFPv4 = 1 << 16
29 hwcap_IDIVA = 1 << 17
30 hwcap_IDIVT = 1 << 18
31 hwcap_VFPD32 = 1 << 19
32 hwcap_LPAE = 1 << 20
33 hwcap_EVTSTRM = 1 << 21
34
35 hwcap2_AES = 1 << 0
36 hwcap2_PMULL = 1 << 1
37 hwcap2_SHA1 = 1 << 2
38 hwcap2_SHA2 = 1 << 3
39 hwcap2_CRC32 = 1 << 4
40)
41
42func initOptions() {
43 options = []option{
44 {Name: "pmull", Feature: &ARM.HasPMULL},
45 {Name: "sha1", Feature: &ARM.HasSHA1},
46 {Name: "sha2", Feature: &ARM.HasSHA2},
47 {Name: "swp", Feature: &ARM.HasSWP},
48 {Name: "thumb", Feature: &ARM.HasTHUMB},
49 {Name: "thumbee", Feature: &ARM.HasTHUMBEE},
50 {Name: "tls", Feature: &ARM.HasTLS},
51 {Name: "vfp", Feature: &ARM.HasVFP},
52 {Name: "vfpd32", Feature: &ARM.HasVFPD32},
53 {Name: "vfpv3", Feature: &ARM.HasVFPv3},
54 {Name: "vfpv3d16", Feature: &ARM.HasVFPv3D16},
55 {Name: "vfpv4", Feature: &ARM.HasVFPv4},
56 {Name: "half", Feature: &ARM.HasHALF},
57 {Name: "26bit", Feature: &ARM.Has26BIT},
58 {Name: "fastmul", Feature: &ARM.HasFASTMUL},
59 {Name: "fpa", Feature: &ARM.HasFPA},
60 {Name: "edsp", Feature: &ARM.HasEDSP},
61 {Name: "java", Feature: &ARM.HasJAVA},
62 {Name: "iwmmxt", Feature: &ARM.HasIWMMXT},
63 {Name: "crunch", Feature: &ARM.HasCRUNCH},
64 {Name: "neon", Feature: &ARM.HasNEON},
65 {Name: "idivt", Feature: &ARM.HasIDIVT},
66 {Name: "idiva", Feature: &ARM.HasIDIVA},
67 {Name: "lpae", Feature: &ARM.HasLPAE},
68 {Name: "evtstrm", Feature: &ARM.HasEVTSTRM},
69 {Name: "aes", Feature: &ARM.HasAES},
70 {Name: "crc32", Feature: &ARM.HasCRC32},
71 }
72
73}
diff --git a/vendor/golang.org/x/sys/cpu/cpu_arm64.go b/vendor/golang.org/x/sys/cpu/cpu_arm64.go
new file mode 100644
index 0000000..f3eb993
--- /dev/null
+++ b/vendor/golang.org/x/sys/cpu/cpu_arm64.go
@@ -0,0 +1,172 @@
1// Copyright 2019 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5package cpu
6
7import "runtime"
8
9// cacheLineSize is used to prevent false sharing of cache lines.
10// We choose 128 because Apple Silicon, a.k.a. M1, has 128-byte cache line size.
11// It doesn't cost much and is much more future-proof.
12const cacheLineSize = 128
13
14func initOptions() {
15 options = []option{
16 {Name: "fp", Feature: &ARM64.HasFP},
17 {Name: "asimd", Feature: &ARM64.HasASIMD},
18 {Name: "evstrm", Feature: &ARM64.HasEVTSTRM},
19 {Name: "aes", Feature: &ARM64.HasAES},
20 {Name: "fphp", Feature: &ARM64.HasFPHP},
21 {Name: "jscvt", Feature: &ARM64.HasJSCVT},
22 {Name: "lrcpc", Feature: &ARM64.HasLRCPC},
23 {Name: "pmull", Feature: &ARM64.HasPMULL},
24 {Name: "sha1", Feature: &ARM64.HasSHA1},
25 {Name: "sha2", Feature: &ARM64.HasSHA2},
26 {Name: "sha3", Feature: &ARM64.HasSHA3},
27 {Name: "sha512", Feature: &ARM64.HasSHA512},
28 {Name: "sm3", Feature: &ARM64.HasSM3},
29 {Name: "sm4", Feature: &ARM64.HasSM4},
30 {Name: "sve", Feature: &ARM64.HasSVE},
31 {Name: "crc32", Feature: &ARM64.HasCRC32},
32 {Name: "atomics", Feature: &ARM64.HasATOMICS},
33 {Name: "asimdhp", Feature: &ARM64.HasASIMDHP},
34 {Name: "cpuid", Feature: &ARM64.HasCPUID},
35 {Name: "asimrdm", Feature: &ARM64.HasASIMDRDM},
36 {Name: "fcma", Feature: &ARM64.HasFCMA},
37 {Name: "dcpop", Feature: &ARM64.HasDCPOP},
38 {Name: "asimddp", Feature: &ARM64.HasASIMDDP},
39 {Name: "asimdfhm", Feature: &ARM64.HasASIMDFHM},
40 }
41}
42
43func archInit() {
44 switch runtime.GOOS {
45 case "freebsd":
46 readARM64Registers()
47 case "linux", "netbsd", "openbsd":
48 doinit()
49 default:
50 // Many platforms don't seem to allow reading these registers.
51 setMinimalFeatures()
52 }
53}
54
55// setMinimalFeatures fakes the minimal ARM64 features expected by
56// TestARM64minimalFeatures.
57func setMinimalFeatures() {
58 ARM64.HasASIMD = true
59 ARM64.HasFP = true
60}
61
62func readARM64Registers() {
63 Initialized = true
64
65 parseARM64SystemRegisters(getisar0(), getisar1(), getpfr0())
66}
67
68func parseARM64SystemRegisters(isar0, isar1, pfr0 uint64) {
69 // ID_AA64ISAR0_EL1
70 switch extractBits(isar0, 4, 7) {
71 case 1:
72 ARM64.HasAES = true
73 case 2:
74 ARM64.HasAES = true
75 ARM64.HasPMULL = true
76 }
77
78 switch extractBits(isar0, 8, 11) {
79 case 1:
80 ARM64.HasSHA1 = true
81 }
82
83 switch extractBits(isar0, 12, 15) {
84 case 1:
85 ARM64.HasSHA2 = true
86 case 2:
87 ARM64.HasSHA2 = true
88 ARM64.HasSHA512 = true
89 }
90
91 switch extractBits(isar0, 16, 19) {
92 case 1:
93 ARM64.HasCRC32 = true
94 }
95
96 switch extractBits(isar0, 20, 23) {
97 case 2:
98 ARM64.HasATOMICS = true
99 }
100
101 switch extractBits(isar0, 28, 31) {
102 case 1:
103 ARM64.HasASIMDRDM = true
104 }
105
106 switch extractBits(isar0, 32, 35) {
107 case 1:
108 ARM64.HasSHA3 = true
109 }
110
111 switch extractBits(isar0, 36, 39) {
112 case 1:
113 ARM64.HasSM3 = true
114 }
115
116 switch extractBits(isar0, 40, 43) {
117 case 1:
118 ARM64.HasSM4 = true
119 }
120
121 switch extractBits(isar0, 44, 47) {
122 case 1:
123 ARM64.HasASIMDDP = true
124 }
125
126 // ID_AA64ISAR1_EL1
127 switch extractBits(isar1, 0, 3) {
128 case 1:
129 ARM64.HasDCPOP = true
130 }
131
132 switch extractBits(isar1, 12, 15) {
133 case 1:
134 ARM64.HasJSCVT = true
135 }
136
137 switch extractBits(isar1, 16, 19) {
138 case 1:
139 ARM64.HasFCMA = true
140 }
141
142 switch extractBits(isar1, 20, 23) {
143 case 1:
144 ARM64.HasLRCPC = true
145 }
146
147 // ID_AA64PFR0_EL1
148 switch extractBits(pfr0, 16, 19) {
149 case 0:
150 ARM64.HasFP = true
151 case 1:
152 ARM64.HasFP = true
153 ARM64.HasFPHP = true
154 }
155
156 switch extractBits(pfr0, 20, 23) {
157 case 0:
158 ARM64.HasASIMD = true
159 case 1:
160 ARM64.HasASIMD = true
161 ARM64.HasASIMDHP = true
162 }
163
164 switch extractBits(pfr0, 32, 35) {
165 case 1:
166 ARM64.HasSVE = true
167 }
168}
169
170func extractBits(data uint64, start, end uint) uint {
171 return (uint)(data>>start) & ((1 << (end - start + 1)) - 1)
172}
diff --git a/vendor/golang.org/x/sys/cpu/cpu_arm64.s b/vendor/golang.org/x/sys/cpu/cpu_arm64.s
new file mode 100644
index 0000000..fcb9a38
--- /dev/null
+++ b/vendor/golang.org/x/sys/cpu/cpu_arm64.s
@@ -0,0 +1,31 @@
1// Copyright 2019 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5//go:build gc
6
7#include "textflag.h"
8
9// func getisar0() uint64
10TEXT ·getisar0(SB),NOSPLIT,$0-8
11 // get Instruction Set Attributes 0 into x0
12 // mrs x0, ID_AA64ISAR0_EL1 = d5380600
13 WORD $0xd5380600
14 MOVD R0, ret+0(FP)
15 RET
16
17// func getisar1() uint64
18TEXT ·getisar1(SB),NOSPLIT,$0-8
19 // get Instruction Set Attributes 1 into x0
20 // mrs x0, ID_AA64ISAR1_EL1 = d5380620
21 WORD $0xd5380620
22 MOVD R0, ret+0(FP)
23 RET
24
25// func getpfr0() uint64
26TEXT ·getpfr0(SB),NOSPLIT,$0-8
27 // get Processor Feature Register 0 into x0
28 // mrs x0, ID_AA64PFR0_EL1 = d5380400
29 WORD $0xd5380400
30 MOVD R0, ret+0(FP)
31 RET
diff --git a/vendor/golang.org/x/sys/cpu/cpu_gc_arm64.go b/vendor/golang.org/x/sys/cpu/cpu_gc_arm64.go
new file mode 100644
index 0000000..a8acd3e
--- /dev/null
+++ b/vendor/golang.org/x/sys/cpu/cpu_gc_arm64.go
@@ -0,0 +1,11 @@
1// Copyright 2019 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5//go:build gc
6
7package cpu
8
9func getisar0() uint64
10func getisar1() uint64
11func getpfr0() uint64
diff --git a/vendor/golang.org/x/sys/cpu/cpu_gc_s390x.go b/vendor/golang.org/x/sys/cpu/cpu_gc_s390x.go
new file mode 100644
index 0000000..c8ae6dd
--- /dev/null
+++ b/vendor/golang.org/x/sys/cpu/cpu_gc_s390x.go
@@ -0,0 +1,21 @@
1// Copyright 2019 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5//go:build gc
6
7package cpu
8
9// haveAsmFunctions reports whether the other functions in this file can
10// be safely called.
11func haveAsmFunctions() bool { return true }
12
13// The following feature detection functions are defined in cpu_s390x.s.
14// They are likely to be expensive to call so the results should be cached.
15func stfle() facilityList
16func kmQuery() queryResult
17func kmcQuery() queryResult
18func kmctrQuery() queryResult
19func kmaQuery() queryResult
20func kimdQuery() queryResult
21func klmdQuery() queryResult
diff --git a/vendor/golang.org/x/sys/cpu/cpu_gc_x86.go b/vendor/golang.org/x/sys/cpu/cpu_gc_x86.go
new file mode 100644
index 0000000..910728f
--- /dev/null
+++ b/vendor/golang.org/x/sys/cpu/cpu_gc_x86.go
@@ -0,0 +1,15 @@
1// Copyright 2018 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5//go:build (386 || amd64 || amd64p32) && gc
6
7package cpu
8
9// cpuid is implemented in cpu_x86.s for gc compiler
10// and in cpu_gccgo.c for gccgo.
11func cpuid(eaxArg, ecxArg uint32) (eax, ebx, ecx, edx uint32)
12
13// xgetbv with ecx = 0 is implemented in cpu_x86.s for gc compiler
14// and in cpu_gccgo.c for gccgo.
15func xgetbv() (eax, edx uint32)
diff --git a/vendor/golang.org/x/sys/cpu/cpu_gccgo_arm64.go b/vendor/golang.org/x/sys/cpu/cpu_gccgo_arm64.go
new file mode 100644
index 0000000..7f19467
--- /dev/null
+++ b/vendor/golang.org/x/sys/cpu/cpu_gccgo_arm64.go
@@ -0,0 +1,11 @@
1// Copyright 2019 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5//go:build gccgo
6
7package cpu
8
9func getisar0() uint64 { return 0 }
10func getisar1() uint64 { return 0 }
11func getpfr0() uint64 { return 0 }
diff --git a/vendor/golang.org/x/sys/cpu/cpu_gccgo_s390x.go b/vendor/golang.org/x/sys/cpu/cpu_gccgo_s390x.go
new file mode 100644
index 0000000..9526d2c
--- /dev/null
+++ b/vendor/golang.org/x/sys/cpu/cpu_gccgo_s390x.go
@@ -0,0 +1,22 @@
1// Copyright 2019 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5//go:build gccgo
6
7package cpu
8
9// haveAsmFunctions reports whether the other functions in this file can
10// be safely called.
11func haveAsmFunctions() bool { return false }
12
13// TODO(mundaym): the following feature detection functions are currently
14// stubs. See https://golang.org/cl/162887 for how to fix this.
15// They are likely to be expensive to call so the results should be cached.
16func stfle() facilityList { panic("not implemented for gccgo") }
17func kmQuery() queryResult { panic("not implemented for gccgo") }
18func kmcQuery() queryResult { panic("not implemented for gccgo") }
19func kmctrQuery() queryResult { panic("not implemented for gccgo") }
20func kmaQuery() queryResult { panic("not implemented for gccgo") }
21func kimdQuery() queryResult { panic("not implemented for gccgo") }
22func klmdQuery() queryResult { panic("not implemented for gccgo") }
diff --git a/vendor/golang.org/x/sys/cpu/cpu_gccgo_x86.c b/vendor/golang.org/x/sys/cpu/cpu_gccgo_x86.c
new file mode 100644
index 0000000..3f73a05
--- /dev/null
+++ b/vendor/golang.org/x/sys/cpu/cpu_gccgo_x86.c
@@ -0,0 +1,37 @@
1// Copyright 2018 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5//go:build (386 || amd64 || amd64p32) && gccgo
6
7#include <cpuid.h>
8#include <stdint.h>
9#include <x86intrin.h>
10
11// Need to wrap __get_cpuid_count because it's declared as static.
12int
13gccgoGetCpuidCount(uint32_t leaf, uint32_t subleaf,
14 uint32_t *eax, uint32_t *ebx,
15 uint32_t *ecx, uint32_t *edx)
16{
17 return __get_cpuid_count(leaf, subleaf, eax, ebx, ecx, edx);
18}
19
20#pragma GCC diagnostic ignored "-Wunknown-pragmas"
21#pragma GCC push_options
22#pragma GCC target("xsave")
23#pragma clang attribute push (__attribute__((target("xsave"))), apply_to=function)
24
25// xgetbv reads the contents of an XCR (Extended Control Register)
26// specified in the ECX register into registers EDX:EAX.
27// Currently, the only supported value for XCR is 0.
28void
29gccgoXgetbv(uint32_t *eax, uint32_t *edx)
30{
31 uint64_t v = _xgetbv(0);
32 *eax = v & 0xffffffff;
33 *edx = v >> 32;
34}
35
36#pragma clang attribute pop
37#pragma GCC pop_options
diff --git a/vendor/golang.org/x/sys/cpu/cpu_gccgo_x86.go b/vendor/golang.org/x/sys/cpu/cpu_gccgo_x86.go
new file mode 100644
index 0000000..99c60fe
--- /dev/null
+++ b/vendor/golang.org/x/sys/cpu/cpu_gccgo_x86.go
@@ -0,0 +1,31 @@
1// Copyright 2018 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5//go:build (386 || amd64 || amd64p32) && gccgo
6
7package cpu
8
9//extern gccgoGetCpuidCount
10func gccgoGetCpuidCount(eaxArg, ecxArg uint32, eax, ebx, ecx, edx *uint32)
11
12func cpuid(eaxArg, ecxArg uint32) (eax, ebx, ecx, edx uint32) {
13 var a, b, c, d uint32
14 gccgoGetCpuidCount(eaxArg, ecxArg, &a, &b, &c, &d)
15 return a, b, c, d
16}
17
18//extern gccgoXgetbv
19func gccgoXgetbv(eax, edx *uint32)
20
21func xgetbv() (eax, edx uint32) {
22 var a, d uint32
23 gccgoXgetbv(&a, &d)
24 return a, d
25}
26
27// gccgo doesn't build on Darwin, per:
28// https://github.com/Homebrew/homebrew-core/blob/HEAD/Formula/gcc.rb#L76
29func darwinSupportsAVX512() bool {
30 return false
31}
diff --git a/vendor/golang.org/x/sys/cpu/cpu_linux.go b/vendor/golang.org/x/sys/cpu/cpu_linux.go
new file mode 100644
index 0000000..743eb54
--- /dev/null
+++ b/vendor/golang.org/x/sys/cpu/cpu_linux.go
@@ -0,0 +1,15 @@
1// Copyright 2018 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5//go:build !386 && !amd64 && !amd64p32 && !arm64
6
7package cpu
8
9func archInit() {
10 if err := readHWCAP(); err != nil {
11 return
12 }
13 doinit()
14 Initialized = true
15}
diff --git a/vendor/golang.org/x/sys/cpu/cpu_linux_arm.go b/vendor/golang.org/x/sys/cpu/cpu_linux_arm.go
new file mode 100644
index 0000000..2057006
--- /dev/null
+++ b/vendor/golang.org/x/sys/cpu/cpu_linux_arm.go
@@ -0,0 +1,39 @@
1// Copyright 2019 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5package cpu
6
7func doinit() {
8 ARM.HasSWP = isSet(hwCap, hwcap_SWP)
9 ARM.HasHALF = isSet(hwCap, hwcap_HALF)
10 ARM.HasTHUMB = isSet(hwCap, hwcap_THUMB)
11 ARM.Has26BIT = isSet(hwCap, hwcap_26BIT)
12 ARM.HasFASTMUL = isSet(hwCap, hwcap_FAST_MULT)
13 ARM.HasFPA = isSet(hwCap, hwcap_FPA)
14 ARM.HasVFP = isSet(hwCap, hwcap_VFP)
15 ARM.HasEDSP = isSet(hwCap, hwcap_EDSP)
16 ARM.HasJAVA = isSet(hwCap, hwcap_JAVA)
17 ARM.HasIWMMXT = isSet(hwCap, hwcap_IWMMXT)
18 ARM.HasCRUNCH = isSet(hwCap, hwcap_CRUNCH)
19 ARM.HasTHUMBEE = isSet(hwCap, hwcap_THUMBEE)
20 ARM.HasNEON = isSet(hwCap, hwcap_NEON)
21 ARM.HasVFPv3 = isSet(hwCap, hwcap_VFPv3)
22 ARM.HasVFPv3D16 = isSet(hwCap, hwcap_VFPv3D16)
23 ARM.HasTLS = isSet(hwCap, hwcap_TLS)
24 ARM.HasVFPv4 = isSet(hwCap, hwcap_VFPv4)
25 ARM.HasIDIVA = isSet(hwCap, hwcap_IDIVA)
26 ARM.HasIDIVT = isSet(hwCap, hwcap_IDIVT)
27 ARM.HasVFPD32 = isSet(hwCap, hwcap_VFPD32)
28 ARM.HasLPAE = isSet(hwCap, hwcap_LPAE)
29 ARM.HasEVTSTRM = isSet(hwCap, hwcap_EVTSTRM)
30 ARM.HasAES = isSet(hwCap2, hwcap2_AES)
31 ARM.HasPMULL = isSet(hwCap2, hwcap2_PMULL)
32 ARM.HasSHA1 = isSet(hwCap2, hwcap2_SHA1)
33 ARM.HasSHA2 = isSet(hwCap2, hwcap2_SHA2)
34 ARM.HasCRC32 = isSet(hwCap2, hwcap2_CRC32)
35}
36
37func isSet(hwc uint, value uint) bool {
38 return hwc&value != 0
39}
diff --git a/vendor/golang.org/x/sys/cpu/cpu_linux_arm64.go b/vendor/golang.org/x/sys/cpu/cpu_linux_arm64.go
new file mode 100644
index 0000000..a968b80
--- /dev/null
+++ b/vendor/golang.org/x/sys/cpu/cpu_linux_arm64.go
@@ -0,0 +1,111 @@
1// Copyright 2018 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5package cpu
6
7import (
8 "strings"
9 "syscall"
10)
11
12// HWCAP/HWCAP2 bits. These are exposed by Linux.
13const (
14 hwcap_FP = 1 << 0
15 hwcap_ASIMD = 1 << 1
16 hwcap_EVTSTRM = 1 << 2
17 hwcap_AES = 1 << 3
18 hwcap_PMULL = 1 << 4
19 hwcap_SHA1 = 1 << 5
20 hwcap_SHA2 = 1 << 6
21 hwcap_CRC32 = 1 << 7
22 hwcap_ATOMICS = 1 << 8
23 hwcap_FPHP = 1 << 9
24 hwcap_ASIMDHP = 1 << 10
25 hwcap_CPUID = 1 << 11
26 hwcap_ASIMDRDM = 1 << 12
27 hwcap_JSCVT = 1 << 13
28 hwcap_FCMA = 1 << 14
29 hwcap_LRCPC = 1 << 15
30 hwcap_DCPOP = 1 << 16
31 hwcap_SHA3 = 1 << 17
32 hwcap_SM3 = 1 << 18
33 hwcap_SM4 = 1 << 19
34 hwcap_ASIMDDP = 1 << 20
35 hwcap_SHA512 = 1 << 21
36 hwcap_SVE = 1 << 22
37 hwcap_ASIMDFHM = 1 << 23
38)
39
40// linuxKernelCanEmulateCPUID reports whether we're running
41// on Linux 4.11+. Ideally we'd like to ask the question about
42// whether the current kernel contains
43// https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=77c97b4ee21290f5f083173d957843b615abbff2
44// but the version number will have to do.
45func linuxKernelCanEmulateCPUID() bool {
46 var un syscall.Utsname
47 syscall.Uname(&un)
48 var sb strings.Builder
49 for _, b := range un.Release[:] {
50 if b == 0 {
51 break
52 }
53 sb.WriteByte(byte(b))
54 }
55 major, minor, _, ok := parseRelease(sb.String())
56 return ok && (major > 4 || major == 4 && minor >= 11)
57}
58
59func doinit() {
60 if err := readHWCAP(); err != nil {
61 // We failed to read /proc/self/auxv. This can happen if the binary has
62 // been given extra capabilities(7) with /bin/setcap.
63 //
64 // When this happens, we have two options. If the Linux kernel is new
65 // enough (4.11+), we can read the arm64 registers directly which'll
66 // trap into the kernel and then return back to userspace.
67 //
68 // But on older kernels, such as Linux 4.4.180 as used on many Synology
69 // devices, calling readARM64Registers (specifically getisar0) will
70 // cause a SIGILL and we'll die. So for older kernels, parse /proc/cpuinfo
71 // instead.
72 //
73 // See golang/go#57336.
74 if linuxKernelCanEmulateCPUID() {
75 readARM64Registers()
76 } else {
77 readLinuxProcCPUInfo()
78 }
79 return
80 }
81
82 // HWCAP feature bits
83 ARM64.HasFP = isSet(hwCap, hwcap_FP)
84 ARM64.HasASIMD = isSet(hwCap, hwcap_ASIMD)
85 ARM64.HasEVTSTRM = isSet(hwCap, hwcap_EVTSTRM)
86 ARM64.HasAES = isSet(hwCap, hwcap_AES)
87 ARM64.HasPMULL = isSet(hwCap, hwcap_PMULL)
88 ARM64.HasSHA1 = isSet(hwCap, hwcap_SHA1)
89 ARM64.HasSHA2 = isSet(hwCap, hwcap_SHA2)
90 ARM64.HasCRC32 = isSet(hwCap, hwcap_CRC32)
91 ARM64.HasATOMICS = isSet(hwCap, hwcap_ATOMICS)
92 ARM64.HasFPHP = isSet(hwCap, hwcap_FPHP)
93 ARM64.HasASIMDHP = isSet(hwCap, hwcap_ASIMDHP)
94 ARM64.HasCPUID = isSet(hwCap, hwcap_CPUID)
95 ARM64.HasASIMDRDM = isSet(hwCap, hwcap_ASIMDRDM)
96 ARM64.HasJSCVT = isSet(hwCap, hwcap_JSCVT)
97 ARM64.HasFCMA = isSet(hwCap, hwcap_FCMA)
98 ARM64.HasLRCPC = isSet(hwCap, hwcap_LRCPC)
99 ARM64.HasDCPOP = isSet(hwCap, hwcap_DCPOP)
100 ARM64.HasSHA3 = isSet(hwCap, hwcap_SHA3)
101 ARM64.HasSM3 = isSet(hwCap, hwcap_SM3)
102 ARM64.HasSM4 = isSet(hwCap, hwcap_SM4)
103 ARM64.HasASIMDDP = isSet(hwCap, hwcap_ASIMDDP)
104 ARM64.HasSHA512 = isSet(hwCap, hwcap_SHA512)
105 ARM64.HasSVE = isSet(hwCap, hwcap_SVE)
106 ARM64.HasASIMDFHM = isSet(hwCap, hwcap_ASIMDFHM)
107}
108
109func isSet(hwc uint, value uint) bool {
110 return hwc&value != 0
111}
diff --git a/vendor/golang.org/x/sys/cpu/cpu_linux_mips64x.go b/vendor/golang.org/x/sys/cpu/cpu_linux_mips64x.go
new file mode 100644
index 0000000..4686c1d
--- /dev/null
+++ b/vendor/golang.org/x/sys/cpu/cpu_linux_mips64x.go
@@ -0,0 +1,22 @@
1// Copyright 2020 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5//go:build linux && (mips64 || mips64le)
6
7package cpu
8
9// HWCAP bits. These are exposed by the Linux kernel 5.4.
10const (
11 // CPU features
12 hwcap_MIPS_MSA = 1 << 1
13)
14
15func doinit() {
16 // HWCAP feature bits
17 MIPS64X.HasMSA = isSet(hwCap, hwcap_MIPS_MSA)
18}
19
20func isSet(hwc uint, value uint) bool {
21 return hwc&value != 0
22}
diff --git a/vendor/golang.org/x/sys/cpu/cpu_linux_noinit.go b/vendor/golang.org/x/sys/cpu/cpu_linux_noinit.go
new file mode 100644
index 0000000..cd63e73
--- /dev/null
+++ b/vendor/golang.org/x/sys/cpu/cpu_linux_noinit.go
@@ -0,0 +1,9 @@
1// Copyright 2019 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5//go:build linux && !arm && !arm64 && !mips64 && !mips64le && !ppc64 && !ppc64le && !s390x
6
7package cpu
8
9func doinit() {}
diff --git a/vendor/golang.org/x/sys/cpu/cpu_linux_ppc64x.go b/vendor/golang.org/x/sys/cpu/cpu_linux_ppc64x.go
new file mode 100644
index 0000000..197188e
--- /dev/null
+++ b/vendor/golang.org/x/sys/cpu/cpu_linux_ppc64x.go
@@ -0,0 +1,30 @@
1// Copyright 2018 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5//go:build linux && (ppc64 || ppc64le)
6
7package cpu
8
9// HWCAP/HWCAP2 bits. These are exposed by the kernel.
10const (
11 // ISA Level
12 _PPC_FEATURE2_ARCH_2_07 = 0x80000000
13 _PPC_FEATURE2_ARCH_3_00 = 0x00800000
14
15 // CPU features
16 _PPC_FEATURE2_DARN = 0x00200000
17 _PPC_FEATURE2_SCV = 0x00100000
18)
19
20func doinit() {
21 // HWCAP2 feature bits
22 PPC64.IsPOWER8 = isSet(hwCap2, _PPC_FEATURE2_ARCH_2_07)
23 PPC64.IsPOWER9 = isSet(hwCap2, _PPC_FEATURE2_ARCH_3_00)
24 PPC64.HasDARN = isSet(hwCap2, _PPC_FEATURE2_DARN)
25 PPC64.HasSCV = isSet(hwCap2, _PPC_FEATURE2_SCV)
26}
27
28func isSet(hwc uint, value uint) bool {
29 return hwc&value != 0
30}
diff --git a/vendor/golang.org/x/sys/cpu/cpu_linux_s390x.go b/vendor/golang.org/x/sys/cpu/cpu_linux_s390x.go
new file mode 100644
index 0000000..1517ac6
--- /dev/null
+++ b/vendor/golang.org/x/sys/cpu/cpu_linux_s390x.go
@@ -0,0 +1,40 @@
1// Copyright 2019 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5package cpu
6
7const (
8 // bit mask values from /usr/include/bits/hwcap.h
9 hwcap_ZARCH = 2
10 hwcap_STFLE = 4
11 hwcap_MSA = 8
12 hwcap_LDISP = 16
13 hwcap_EIMM = 32
14 hwcap_DFP = 64
15 hwcap_ETF3EH = 256
16 hwcap_VX = 2048
17 hwcap_VXE = 8192
18)
19
20func initS390Xbase() {
21 // test HWCAP bit vector
22 has := func(featureMask uint) bool {
23 return hwCap&featureMask == featureMask
24 }
25
26 // mandatory
27 S390X.HasZARCH = has(hwcap_ZARCH)
28
29 // optional
30 S390X.HasSTFLE = has(hwcap_STFLE)
31 S390X.HasLDISP = has(hwcap_LDISP)
32 S390X.HasEIMM = has(hwcap_EIMM)
33 S390X.HasETF3EH = has(hwcap_ETF3EH)
34 S390X.HasDFP = has(hwcap_DFP)
35 S390X.HasMSA = has(hwcap_MSA)
36 S390X.HasVX = has(hwcap_VX)
37 if S390X.HasVX {
38 S390X.HasVXE = has(hwcap_VXE)
39 }
40}
diff --git a/vendor/golang.org/x/sys/cpu/cpu_loong64.go b/vendor/golang.org/x/sys/cpu/cpu_loong64.go
new file mode 100644
index 0000000..5586358
--- /dev/null
+++ b/vendor/golang.org/x/sys/cpu/cpu_loong64.go
@@ -0,0 +1,12 @@
1// Copyright 2022 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5//go:build loong64
6
7package cpu
8
9const cacheLineSize = 64
10
11func initOptions() {
12}
diff --git a/vendor/golang.org/x/sys/cpu/cpu_mips64x.go b/vendor/golang.org/x/sys/cpu/cpu_mips64x.go
new file mode 100644
index 0000000..fedb00c
--- /dev/null
+++ b/vendor/golang.org/x/sys/cpu/cpu_mips64x.go
@@ -0,0 +1,15 @@
1// Copyright 2018 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5//go:build mips64 || mips64le
6
7package cpu
8
9const cacheLineSize = 32
10
11func initOptions() {
12 options = []option{
13 {Name: "msa", Feature: &MIPS64X.HasMSA},
14 }
15}
diff --git a/vendor/golang.org/x/sys/cpu/cpu_mipsx.go b/vendor/golang.org/x/sys/cpu/cpu_mipsx.go
new file mode 100644
index 0000000..ffb4ec7
--- /dev/null
+++ b/vendor/golang.org/x/sys/cpu/cpu_mipsx.go
@@ -0,0 +1,11 @@
1// Copyright 2018 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5//go:build mips || mipsle
6
7package cpu
8
9const cacheLineSize = 32
10
11func initOptions() {}
diff --git a/vendor/golang.org/x/sys/cpu/cpu_netbsd_arm64.go b/vendor/golang.org/x/sys/cpu/cpu_netbsd_arm64.go
new file mode 100644
index 0000000..ebfb3fc
--- /dev/null
+++ b/vendor/golang.org/x/sys/cpu/cpu_netbsd_arm64.go
@@ -0,0 +1,173 @@
1// Copyright 2020 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5package cpu
6
7import (
8 "syscall"
9 "unsafe"
10)
11
12// Minimal copy of functionality from x/sys/unix so the cpu package can call
13// sysctl without depending on x/sys/unix.
14
15const (
16 _CTL_QUERY = -2
17
18 _SYSCTL_VERS_1 = 0x1000000
19)
20
21var _zero uintptr
22
23func sysctl(mib []int32, old *byte, oldlen *uintptr, new *byte, newlen uintptr) (err error) {
24 var _p0 unsafe.Pointer
25 if len(mib) > 0 {
26 _p0 = unsafe.Pointer(&mib[0])
27 } else {
28 _p0 = unsafe.Pointer(&_zero)
29 }
30 _, _, errno := syscall.Syscall6(
31 syscall.SYS___SYSCTL,
32 uintptr(_p0),
33 uintptr(len(mib)),
34 uintptr(unsafe.Pointer(old)),
35 uintptr(unsafe.Pointer(oldlen)),
36 uintptr(unsafe.Pointer(new)),
37 uintptr(newlen))
38 if errno != 0 {
39 return errno
40 }
41 return nil
42}
43
44type sysctlNode struct {
45 Flags uint32
46 Num int32
47 Name [32]int8
48 Ver uint32
49 __rsvd uint32
50 Un [16]byte
51 _sysctl_size [8]byte
52 _sysctl_func [8]byte
53 _sysctl_parent [8]byte
54 _sysctl_desc [8]byte
55}
56
57func sysctlNodes(mib []int32) ([]sysctlNode, error) {
58 var olen uintptr
59
60 // Get a list of all sysctl nodes below the given MIB by performing
61 // a sysctl for the given MIB with CTL_QUERY appended.
62 mib = append(mib, _CTL_QUERY)
63 qnode := sysctlNode{Flags: _SYSCTL_VERS_1}
64 qp := (*byte)(unsafe.Pointer(&qnode))
65 sz := unsafe.Sizeof(qnode)
66 if err := sysctl(mib, nil, &olen, qp, sz); err != nil {
67 return nil, err
68 }
69
70 // Now that we know the size, get the actual nodes.
71 nodes := make([]sysctlNode, olen/sz)
72 np := (*byte)(unsafe.Pointer(&nodes[0]))
73 if err := sysctl(mib, np, &olen, qp, sz); err != nil {
74 return nil, err
75 }
76
77 return nodes, nil
78}
79
80func nametomib(name string) ([]int32, error) {
81 // Split name into components.
82 var parts []string
83 last := 0
84 for i := 0; i < len(name); i++ {
85 if name[i] == '.' {
86 parts = append(parts, name[last:i])
87 last = i + 1
88 }
89 }
90 parts = append(parts, name[last:])
91
92 mib := []int32{}
93 // Discover the nodes and construct the MIB OID.
94 for partno, part := range parts {
95 nodes, err := sysctlNodes(mib)
96 if err != nil {
97 return nil, err
98 }
99 for _, node := range nodes {
100 n := make([]byte, 0)
101 for i := range node.Name {
102 if node.Name[i] != 0 {
103 n = append(n, byte(node.Name[i]))
104 }
105 }
106 if string(n) == part {
107 mib = append(mib, int32(node.Num))
108 break
109 }
110 }
111 if len(mib) != partno+1 {
112 return nil, err
113 }
114 }
115
116 return mib, nil
117}
118
119// aarch64SysctlCPUID is struct aarch64_sysctl_cpu_id from NetBSD's <aarch64/armreg.h>
120type aarch64SysctlCPUID struct {
121 midr uint64 /* Main ID Register */
122 revidr uint64 /* Revision ID Register */
123 mpidr uint64 /* Multiprocessor Affinity Register */
124 aa64dfr0 uint64 /* A64 Debug Feature Register 0 */
125 aa64dfr1 uint64 /* A64 Debug Feature Register 1 */
126 aa64isar0 uint64 /* A64 Instruction Set Attribute Register 0 */
127 aa64isar1 uint64 /* A64 Instruction Set Attribute Register 1 */
128 aa64mmfr0 uint64 /* A64 Memory Model Feature Register 0 */
129 aa64mmfr1 uint64 /* A64 Memory Model Feature Register 1 */
130 aa64mmfr2 uint64 /* A64 Memory Model Feature Register 2 */
131 aa64pfr0 uint64 /* A64 Processor Feature Register 0 */
132 aa64pfr1 uint64 /* A64 Processor Feature Register 1 */
133 aa64zfr0 uint64 /* A64 SVE Feature ID Register 0 */
134 mvfr0 uint32 /* Media and VFP Feature Register 0 */
135 mvfr1 uint32 /* Media and VFP Feature Register 1 */
136 mvfr2 uint32 /* Media and VFP Feature Register 2 */
137 pad uint32
138 clidr uint64 /* Cache Level ID Register */
139 ctr uint64 /* Cache Type Register */
140}
141
142func sysctlCPUID(name string) (*aarch64SysctlCPUID, error) {
143 mib, err := nametomib(name)
144 if err != nil {
145 return nil, err
146 }
147
148 out := aarch64SysctlCPUID{}
149 n := unsafe.Sizeof(out)
150 _, _, errno := syscall.Syscall6(
151 syscall.SYS___SYSCTL,
152 uintptr(unsafe.Pointer(&mib[0])),
153 uintptr(len(mib)),
154 uintptr(unsafe.Pointer(&out)),
155 uintptr(unsafe.Pointer(&n)),
156 uintptr(0),
157 uintptr(0))
158 if errno != 0 {
159 return nil, errno
160 }
161 return &out, nil
162}
163
164func doinit() {
165 cpuid, err := sysctlCPUID("machdep.cpu0.cpu_id")
166 if err != nil {
167 setMinimalFeatures()
168 return
169 }
170 parseARM64SystemRegisters(cpuid.aa64isar0, cpuid.aa64isar1, cpuid.aa64pfr0)
171
172 Initialized = true
173}
diff --git a/vendor/golang.org/x/sys/cpu/cpu_openbsd_arm64.go b/vendor/golang.org/x/sys/cpu/cpu_openbsd_arm64.go
new file mode 100644
index 0000000..85b64d5
--- /dev/null
+++ b/vendor/golang.org/x/sys/cpu/cpu_openbsd_arm64.go
@@ -0,0 +1,65 @@
1// Copyright 2022 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5package cpu
6
7import (
8 "syscall"
9 "unsafe"
10)
11
12// Minimal copy of functionality from x/sys/unix so the cpu package can call
13// sysctl without depending on x/sys/unix.
14
15const (
16 // From OpenBSD's sys/sysctl.h.
17 _CTL_MACHDEP = 7
18
19 // From OpenBSD's machine/cpu.h.
20 _CPU_ID_AA64ISAR0 = 2
21 _CPU_ID_AA64ISAR1 = 3
22)
23
24// Implemented in the runtime package (runtime/sys_openbsd3.go)
25func syscall_syscall6(fn, a1, a2, a3, a4, a5, a6 uintptr) (r1, r2 uintptr, err syscall.Errno)
26
27//go:linkname syscall_syscall6 syscall.syscall6
28
29func sysctl(mib []uint32, old *byte, oldlen *uintptr, new *byte, newlen uintptr) (err error) {
30 _, _, errno := syscall_syscall6(libc_sysctl_trampoline_addr, uintptr(unsafe.Pointer(&mib[0])), uintptr(len(mib)), uintptr(unsafe.Pointer(old)), uintptr(unsafe.Pointer(oldlen)), uintptr(unsafe.Pointer(new)), uintptr(newlen))
31 if errno != 0 {
32 return errno
33 }
34 return nil
35}
36
37var libc_sysctl_trampoline_addr uintptr
38
39//go:cgo_import_dynamic libc_sysctl sysctl "libc.so"
40
41func sysctlUint64(mib []uint32) (uint64, bool) {
42 var out uint64
43 nout := unsafe.Sizeof(out)
44 if err := sysctl(mib, (*byte)(unsafe.Pointer(&out)), &nout, nil, 0); err != nil {
45 return 0, false
46 }
47 return out, true
48}
49
50func doinit() {
51 setMinimalFeatures()
52
53 // Get ID_AA64ISAR0 and ID_AA64ISAR1 from sysctl.
54 isar0, ok := sysctlUint64([]uint32{_CTL_MACHDEP, _CPU_ID_AA64ISAR0})
55 if !ok {
56 return
57 }
58 isar1, ok := sysctlUint64([]uint32{_CTL_MACHDEP, _CPU_ID_AA64ISAR1})
59 if !ok {
60 return
61 }
62 parseARM64SystemRegisters(isar0, isar1, 0)
63
64 Initialized = true
65}
diff --git a/vendor/golang.org/x/sys/cpu/cpu_openbsd_arm64.s b/vendor/golang.org/x/sys/cpu/cpu_openbsd_arm64.s
new file mode 100644
index 0000000..054ba05
--- /dev/null
+++ b/vendor/golang.org/x/sys/cpu/cpu_openbsd_arm64.s
@@ -0,0 +1,11 @@
1// Copyright 2022 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5#include "textflag.h"
6
7TEXT libc_sysctl_trampoline<>(SB),NOSPLIT,$0-0
8 JMP libc_sysctl(SB)
9
10GLOBL ·libc_sysctl_trampoline_addr(SB), RODATA, $8
11DATA ·libc_sysctl_trampoline_addr(SB)/8, $libc_sysctl_trampoline<>(SB)
diff --git a/vendor/golang.org/x/sys/cpu/cpu_other_arm.go b/vendor/golang.org/x/sys/cpu/cpu_other_arm.go
new file mode 100644
index 0000000..e9ecf2a
--- /dev/null
+++ b/vendor/golang.org/x/sys/cpu/cpu_other_arm.go
@@ -0,0 +1,9 @@
1// Copyright 2020 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5//go:build !linux && arm
6
7package cpu
8
9func archInit() {}
diff --git a/vendor/golang.org/x/sys/cpu/cpu_other_arm64.go b/vendor/golang.org/x/sys/cpu/cpu_other_arm64.go
new file mode 100644
index 0000000..5341e7f
--- /dev/null
+++ b/vendor/golang.org/x/sys/cpu/cpu_other_arm64.go
@@ -0,0 +1,9 @@
1// Copyright 2019 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5//go:build !linux && !netbsd && !openbsd && arm64
6
7package cpu
8
9func doinit() {}
diff --git a/vendor/golang.org/x/sys/cpu/cpu_other_mips64x.go b/vendor/golang.org/x/sys/cpu/cpu_other_mips64x.go
new file mode 100644
index 0000000..5f8f241
--- /dev/null
+++ b/vendor/golang.org/x/sys/cpu/cpu_other_mips64x.go
@@ -0,0 +1,11 @@
1// Copyright 2020 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5//go:build !linux && (mips64 || mips64le)
6
7package cpu
8
9func archInit() {
10 Initialized = true
11}
diff --git a/vendor/golang.org/x/sys/cpu/cpu_other_ppc64x.go b/vendor/golang.org/x/sys/cpu/cpu_other_ppc64x.go
new file mode 100644
index 0000000..89608fb
--- /dev/null
+++ b/vendor/golang.org/x/sys/cpu/cpu_other_ppc64x.go
@@ -0,0 +1,12 @@
1// Copyright 2022 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5//go:build !aix && !linux && (ppc64 || ppc64le)
6
7package cpu
8
9func archInit() {
10 PPC64.IsPOWER8 = true
11 Initialized = true
12}
diff --git a/vendor/golang.org/x/sys/cpu/cpu_other_riscv64.go b/vendor/golang.org/x/sys/cpu/cpu_other_riscv64.go
new file mode 100644
index 0000000..5ab8780
--- /dev/null
+++ b/vendor/golang.org/x/sys/cpu/cpu_other_riscv64.go
@@ -0,0 +1,11 @@
1// Copyright 2022 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5//go:build !linux && riscv64
6
7package cpu
8
9func archInit() {
10 Initialized = true
11}
diff --git a/vendor/golang.org/x/sys/cpu/cpu_ppc64x.go b/vendor/golang.org/x/sys/cpu/cpu_ppc64x.go
new file mode 100644
index 0000000..c14f12b
--- /dev/null
+++ b/vendor/golang.org/x/sys/cpu/cpu_ppc64x.go
@@ -0,0 +1,16 @@
1// Copyright 2020 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5//go:build ppc64 || ppc64le
6
7package cpu
8
9const cacheLineSize = 128
10
11func initOptions() {
12 options = []option{
13 {Name: "darn", Feature: &PPC64.HasDARN},
14 {Name: "scv", Feature: &PPC64.HasSCV},
15 }
16}
diff --git a/vendor/golang.org/x/sys/cpu/cpu_riscv64.go b/vendor/golang.org/x/sys/cpu/cpu_riscv64.go
new file mode 100644
index 0000000..7f0c79c
--- /dev/null
+++ b/vendor/golang.org/x/sys/cpu/cpu_riscv64.go
@@ -0,0 +1,11 @@
1// Copyright 2019 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5//go:build riscv64
6
7package cpu
8
9const cacheLineSize = 64
10
11func initOptions() {}
diff --git a/vendor/golang.org/x/sys/cpu/cpu_s390x.go b/vendor/golang.org/x/sys/cpu/cpu_s390x.go
new file mode 100644
index 0000000..5881b88
--- /dev/null
+++ b/vendor/golang.org/x/sys/cpu/cpu_s390x.go
@@ -0,0 +1,172 @@
1// Copyright 2020 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5package cpu
6
7const cacheLineSize = 256
8
9func initOptions() {
10 options = []option{
11 {Name: "zarch", Feature: &S390X.HasZARCH, Required: true},
12 {Name: "stfle", Feature: &S390X.HasSTFLE, Required: true},
13 {Name: "ldisp", Feature: &S390X.HasLDISP, Required: true},
14 {Name: "eimm", Feature: &S390X.HasEIMM, Required: true},
15 {Name: "dfp", Feature: &S390X.HasDFP},
16 {Name: "etf3eh", Feature: &S390X.HasETF3EH},
17 {Name: "msa", Feature: &S390X.HasMSA},
18 {Name: "aes", Feature: &S390X.HasAES},
19 {Name: "aescbc", Feature: &S390X.HasAESCBC},
20 {Name: "aesctr", Feature: &S390X.HasAESCTR},
21 {Name: "aesgcm", Feature: &S390X.HasAESGCM},
22 {Name: "ghash", Feature: &S390X.HasGHASH},
23 {Name: "sha1", Feature: &S390X.HasSHA1},
24 {Name: "sha256", Feature: &S390X.HasSHA256},
25 {Name: "sha3", Feature: &S390X.HasSHA3},
26 {Name: "sha512", Feature: &S390X.HasSHA512},
27 {Name: "vx", Feature: &S390X.HasVX},
28 {Name: "vxe", Feature: &S390X.HasVXE},
29 }
30}
31
32// bitIsSet reports whether the bit at index is set. The bit index
33// is in big endian order, so bit index 0 is the leftmost bit.
34func bitIsSet(bits []uint64, index uint) bool {
35 return bits[index/64]&((1<<63)>>(index%64)) != 0
36}
37
38// facility is a bit index for the named facility.
39type facility uint8
40
41const (
42 // mandatory facilities
43 zarch facility = 1 // z architecture mode is active
44 stflef facility = 7 // store-facility-list-extended
45 ldisp facility = 18 // long-displacement
46 eimm facility = 21 // extended-immediate
47
48 // miscellaneous facilities
49 dfp facility = 42 // decimal-floating-point
50 etf3eh facility = 30 // extended-translation 3 enhancement
51
52 // cryptography facilities
53 msa facility = 17 // message-security-assist
54 msa3 facility = 76 // message-security-assist extension 3
55 msa4 facility = 77 // message-security-assist extension 4
56 msa5 facility = 57 // message-security-assist extension 5
57 msa8 facility = 146 // message-security-assist extension 8
58 msa9 facility = 155 // message-security-assist extension 9
59
60 // vector facilities
61 vx facility = 129 // vector facility
62 vxe facility = 135 // vector-enhancements 1
63 vxe2 facility = 148 // vector-enhancements 2
64)
65
66// facilityList contains the result of an STFLE call.
67// Bits are numbered in big endian order so the
68// leftmost bit (the MSB) is at index 0.
69type facilityList struct {
70 bits [4]uint64
71}
72
73// Has reports whether the given facilities are present.
74func (s *facilityList) Has(fs ...facility) bool {
75 if len(fs) == 0 {
76 panic("no facility bits provided")
77 }
78 for _, f := range fs {
79 if !bitIsSet(s.bits[:], uint(f)) {
80 return false
81 }
82 }
83 return true
84}
85
86// function is the code for the named cryptographic function.
87type function uint8
88
89const (
90 // KM{,A,C,CTR} function codes
91 aes128 function = 18 // AES-128
92 aes192 function = 19 // AES-192
93 aes256 function = 20 // AES-256
94
95 // K{I,L}MD function codes
96 sha1 function = 1 // SHA-1
97 sha256 function = 2 // SHA-256
98 sha512 function = 3 // SHA-512
99 sha3_224 function = 32 // SHA3-224
100 sha3_256 function = 33 // SHA3-256
101 sha3_384 function = 34 // SHA3-384
102 sha3_512 function = 35 // SHA3-512
103 shake128 function = 36 // SHAKE-128
104 shake256 function = 37 // SHAKE-256
105
106 // KLMD function codes
107 ghash function = 65 // GHASH
108)
109
110// queryResult contains the result of a Query function
111// call. Bits are numbered in big endian order so the
112// leftmost bit (the MSB) is at index 0.
113type queryResult struct {
114 bits [2]uint64
115}
116
117// Has reports whether the given functions are present.
118func (q *queryResult) Has(fns ...function) bool {
119 if len(fns) == 0 {
120 panic("no function codes provided")
121 }
122 for _, f := range fns {
123 if !bitIsSet(q.bits[:], uint(f)) {
124 return false
125 }
126 }
127 return true
128}
129
130func doinit() {
131 initS390Xbase()
132
133 // We need implementations of stfle, km and so on
134 // to detect cryptographic features.
135 if !haveAsmFunctions() {
136 return
137 }
138
139 // optional cryptographic functions
140 if S390X.HasMSA {
141 aes := []function{aes128, aes192, aes256}
142
143 // cipher message
144 km, kmc := kmQuery(), kmcQuery()
145 S390X.HasAES = km.Has(aes...)
146 S390X.HasAESCBC = kmc.Has(aes...)
147 if S390X.HasSTFLE {
148 facilities := stfle()
149 if facilities.Has(msa4) {
150 kmctr := kmctrQuery()
151 S390X.HasAESCTR = kmctr.Has(aes...)
152 }
153 if facilities.Has(msa8) {
154 kma := kmaQuery()
155 S390X.HasAESGCM = kma.Has(aes...)
156 }
157 }
158
159 // compute message digest
160 kimd := kimdQuery() // intermediate (no padding)
161 klmd := klmdQuery() // last (padding)
162 S390X.HasSHA1 = kimd.Has(sha1) && klmd.Has(sha1)
163 S390X.HasSHA256 = kimd.Has(sha256) && klmd.Has(sha256)
164 S390X.HasSHA512 = kimd.Has(sha512) && klmd.Has(sha512)
165 S390X.HasGHASH = kimd.Has(ghash) // KLMD-GHASH does not exist
166 sha3 := []function{
167 sha3_224, sha3_256, sha3_384, sha3_512,
168 shake128, shake256,
169 }
170 S390X.HasSHA3 = kimd.Has(sha3...) && klmd.Has(sha3...)
171 }
172}
diff --git a/vendor/golang.org/x/sys/cpu/cpu_s390x.s b/vendor/golang.org/x/sys/cpu/cpu_s390x.s
new file mode 100644
index 0000000..1fb4b70
--- /dev/null
+++ b/vendor/golang.org/x/sys/cpu/cpu_s390x.s
@@ -0,0 +1,57 @@
1// Copyright 2019 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5//go:build gc
6
7#include "textflag.h"
8
9// func stfle() facilityList
10TEXT ·stfle(SB), NOSPLIT|NOFRAME, $0-32
11 MOVD $ret+0(FP), R1
12 MOVD $3, R0 // last doubleword index to store
13 XC $32, (R1), (R1) // clear 4 doublewords (32 bytes)
14 WORD $0xb2b01000 // store facility list extended (STFLE)
15 RET
16
17// func kmQuery() queryResult
18TEXT ·kmQuery(SB), NOSPLIT|NOFRAME, $0-16
19 MOVD $0, R0 // set function code to 0 (KM-Query)
20 MOVD $ret+0(FP), R1 // address of 16-byte return value
21 WORD $0xB92E0024 // cipher message (KM)
22 RET
23
24// func kmcQuery() queryResult
25TEXT ·kmcQuery(SB), NOSPLIT|NOFRAME, $0-16
26 MOVD $0, R0 // set function code to 0 (KMC-Query)
27 MOVD $ret+0(FP), R1 // address of 16-byte return value
28 WORD $0xB92F0024 // cipher message with chaining (KMC)
29 RET
30
31// func kmctrQuery() queryResult
32TEXT ·kmctrQuery(SB), NOSPLIT|NOFRAME, $0-16
33 MOVD $0, R0 // set function code to 0 (KMCTR-Query)
34 MOVD $ret+0(FP), R1 // address of 16-byte return value
35 WORD $0xB92D4024 // cipher message with counter (KMCTR)
36 RET
37
38// func kmaQuery() queryResult
39TEXT ·kmaQuery(SB), NOSPLIT|NOFRAME, $0-16
40 MOVD $0, R0 // set function code to 0 (KMA-Query)
41 MOVD $ret+0(FP), R1 // address of 16-byte return value
42 WORD $0xb9296024 // cipher message with authentication (KMA)
43 RET
44
45// func kimdQuery() queryResult
46TEXT ·kimdQuery(SB), NOSPLIT|NOFRAME, $0-16
47 MOVD $0, R0 // set function code to 0 (KIMD-Query)
48 MOVD $ret+0(FP), R1 // address of 16-byte return value
49 WORD $0xB93E0024 // compute intermediate message digest (KIMD)
50 RET
51
52// func klmdQuery() queryResult
53TEXT ·klmdQuery(SB), NOSPLIT|NOFRAME, $0-16
54 MOVD $0, R0 // set function code to 0 (KLMD-Query)
55 MOVD $ret+0(FP), R1 // address of 16-byte return value
56 WORD $0xB93F0024 // compute last message digest (KLMD)
57 RET
diff --git a/vendor/golang.org/x/sys/cpu/cpu_wasm.go b/vendor/golang.org/x/sys/cpu/cpu_wasm.go
new file mode 100644
index 0000000..384787e
--- /dev/null
+++ b/vendor/golang.org/x/sys/cpu/cpu_wasm.go
@@ -0,0 +1,17 @@
1// Copyright 2019 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5//go:build wasm
6
7package cpu
8
9// We're compiling the cpu package for an unknown (software-abstracted) CPU.
10// Make CacheLinePad an empty struct and hope that the usual struct alignment
11// rules are good enough.
12
13const cacheLineSize = 0
14
15func initOptions() {}
16
17func archInit() {}
diff --git a/vendor/golang.org/x/sys/cpu/cpu_x86.go b/vendor/golang.org/x/sys/cpu/cpu_x86.go
new file mode 100644
index 0000000..c29f5e4
--- /dev/null
+++ b/vendor/golang.org/x/sys/cpu/cpu_x86.go
@@ -0,0 +1,151 @@
1// Copyright 2018 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5//go:build 386 || amd64 || amd64p32
6
7package cpu
8
9import "runtime"
10
11const cacheLineSize = 64
12
13func initOptions() {
14 options = []option{
15 {Name: "adx", Feature: &X86.HasADX},
16 {Name: "aes", Feature: &X86.HasAES},
17 {Name: "avx", Feature: &X86.HasAVX},
18 {Name: "avx2", Feature: &X86.HasAVX2},
19 {Name: "avx512", Feature: &X86.HasAVX512},
20 {Name: "avx512f", Feature: &X86.HasAVX512F},
21 {Name: "avx512cd", Feature: &X86.HasAVX512CD},
22 {Name: "avx512er", Feature: &X86.HasAVX512ER},
23 {Name: "avx512pf", Feature: &X86.HasAVX512PF},
24 {Name: "avx512vl", Feature: &X86.HasAVX512VL},
25 {Name: "avx512bw", Feature: &X86.HasAVX512BW},
26 {Name: "avx512dq", Feature: &X86.HasAVX512DQ},
27 {Name: "avx512ifma", Feature: &X86.HasAVX512IFMA},
28 {Name: "avx512vbmi", Feature: &X86.HasAVX512VBMI},
29 {Name: "avx512vnniw", Feature: &X86.HasAVX5124VNNIW},
30 {Name: "avx5124fmaps", Feature: &X86.HasAVX5124FMAPS},
31 {Name: "avx512vpopcntdq", Feature: &X86.HasAVX512VPOPCNTDQ},
32 {Name: "avx512vpclmulqdq", Feature: &X86.HasAVX512VPCLMULQDQ},
33 {Name: "avx512vnni", Feature: &X86.HasAVX512VNNI},
34 {Name: "avx512gfni", Feature: &X86.HasAVX512GFNI},
35 {Name: "avx512vaes", Feature: &X86.HasAVX512VAES},
36 {Name: "avx512vbmi2", Feature: &X86.HasAVX512VBMI2},
37 {Name: "avx512bitalg", Feature: &X86.HasAVX512BITALG},
38 {Name: "avx512bf16", Feature: &X86.HasAVX512BF16},
39 {Name: "amxtile", Feature: &X86.HasAMXTile},
40 {Name: "amxint8", Feature: &X86.HasAMXInt8},
41 {Name: "amxbf16", Feature: &X86.HasAMXBF16},
42 {Name: "bmi1", Feature: &X86.HasBMI1},
43 {Name: "bmi2", Feature: &X86.HasBMI2},
44 {Name: "cx16", Feature: &X86.HasCX16},
45 {Name: "erms", Feature: &X86.HasERMS},
46 {Name: "fma", Feature: &X86.HasFMA},
47 {Name: "osxsave", Feature: &X86.HasOSXSAVE},
48 {Name: "pclmulqdq", Feature: &X86.HasPCLMULQDQ},
49 {Name: "popcnt", Feature: &X86.HasPOPCNT},
50 {Name: "rdrand", Feature: &X86.HasRDRAND},
51 {Name: "rdseed", Feature: &X86.HasRDSEED},
52 {Name: "sse3", Feature: &X86.HasSSE3},
53 {Name: "sse41", Feature: &X86.HasSSE41},
54 {Name: "sse42", Feature: &X86.HasSSE42},
55 {Name: "ssse3", Feature: &X86.HasSSSE3},
56
57 // These capabilities should always be enabled on amd64:
58 {Name: "sse2", Feature: &X86.HasSSE2, Required: runtime.GOARCH == "amd64"},
59 }
60}
61
62func archInit() {
63
64 Initialized = true
65
66 maxID, _, _, _ := cpuid(0, 0)
67
68 if maxID < 1 {
69 return
70 }
71
72 _, _, ecx1, edx1 := cpuid(1, 0)
73 X86.HasSSE2 = isSet(26, edx1)
74
75 X86.HasSSE3 = isSet(0, ecx1)
76 X86.HasPCLMULQDQ = isSet(1, ecx1)
77 X86.HasSSSE3 = isSet(9, ecx1)
78 X86.HasFMA = isSet(12, ecx1)
79 X86.HasCX16 = isSet(13, ecx1)
80 X86.HasSSE41 = isSet(19, ecx1)
81 X86.HasSSE42 = isSet(20, ecx1)
82 X86.HasPOPCNT = isSet(23, ecx1)
83 X86.HasAES = isSet(25, ecx1)
84 X86.HasOSXSAVE = isSet(27, ecx1)
85 X86.HasRDRAND = isSet(30, ecx1)
86
87 var osSupportsAVX, osSupportsAVX512 bool
88 // For XGETBV, OSXSAVE bit is required and sufficient.
89 if X86.HasOSXSAVE {
90 eax, _ := xgetbv()
91 // Check if XMM and YMM registers have OS support.
92 osSupportsAVX = isSet(1, eax) && isSet(2, eax)
93
94 if runtime.GOOS == "darwin" {
95 // Darwin doesn't save/restore AVX-512 mask registers correctly across signal handlers.
96 // Since users can't rely on mask register contents, let's not advertise AVX-512 support.
97 // See issue 49233.
98 osSupportsAVX512 = false
99 } else {
100 // Check if OPMASK and ZMM registers have OS support.
101 osSupportsAVX512 = osSupportsAVX && isSet(5, eax) && isSet(6, eax) && isSet(7, eax)
102 }
103 }
104
105 X86.HasAVX = isSet(28, ecx1) && osSupportsAVX
106
107 if maxID < 7 {
108 return
109 }
110
111 _, ebx7, ecx7, edx7 := cpuid(7, 0)
112 X86.HasBMI1 = isSet(3, ebx7)
113 X86.HasAVX2 = isSet(5, ebx7) && osSupportsAVX
114 X86.HasBMI2 = isSet(8, ebx7)
115 X86.HasERMS = isSet(9, ebx7)
116 X86.HasRDSEED = isSet(18, ebx7)
117 X86.HasADX = isSet(19, ebx7)
118
119 X86.HasAVX512 = isSet(16, ebx7) && osSupportsAVX512 // Because avx-512 foundation is the core required extension
120 if X86.HasAVX512 {
121 X86.HasAVX512F = true
122 X86.HasAVX512CD = isSet(28, ebx7)
123 X86.HasAVX512ER = isSet(27, ebx7)
124 X86.HasAVX512PF = isSet(26, ebx7)
125 X86.HasAVX512VL = isSet(31, ebx7)
126 X86.HasAVX512BW = isSet(30, ebx7)
127 X86.HasAVX512DQ = isSet(17, ebx7)
128 X86.HasAVX512IFMA = isSet(21, ebx7)
129 X86.HasAVX512VBMI = isSet(1, ecx7)
130 X86.HasAVX5124VNNIW = isSet(2, edx7)
131 X86.HasAVX5124FMAPS = isSet(3, edx7)
132 X86.HasAVX512VPOPCNTDQ = isSet(14, ecx7)
133 X86.HasAVX512VPCLMULQDQ = isSet(10, ecx7)
134 X86.HasAVX512VNNI = isSet(11, ecx7)
135 X86.HasAVX512GFNI = isSet(8, ecx7)
136 X86.HasAVX512VAES = isSet(9, ecx7)
137 X86.HasAVX512VBMI2 = isSet(6, ecx7)
138 X86.HasAVX512BITALG = isSet(12, ecx7)
139
140 eax71, _, _, _ := cpuid(7, 1)
141 X86.HasAVX512BF16 = isSet(5, eax71)
142 }
143
144 X86.HasAMXTile = isSet(24, edx7)
145 X86.HasAMXInt8 = isSet(25, edx7)
146 X86.HasAMXBF16 = isSet(22, edx7)
147}
148
149func isSet(bitpos uint, value uint32) bool {
150 return value&(1<<bitpos) != 0
151}
diff --git a/vendor/golang.org/x/sys/cpu/cpu_x86.s b/vendor/golang.org/x/sys/cpu/cpu_x86.s
new file mode 100644
index 0000000..7d7ba33
--- /dev/null
+++ b/vendor/golang.org/x/sys/cpu/cpu_x86.s
@@ -0,0 +1,26 @@
1// Copyright 2018 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5//go:build (386 || amd64 || amd64p32) && gc
6
7#include "textflag.h"
8
9// func cpuid(eaxArg, ecxArg uint32) (eax, ebx, ecx, edx uint32)
10TEXT ·cpuid(SB), NOSPLIT, $0-24
11 MOVL eaxArg+0(FP), AX
12 MOVL ecxArg+4(FP), CX
13 CPUID
14 MOVL AX, eax+8(FP)
15 MOVL BX, ebx+12(FP)
16 MOVL CX, ecx+16(FP)
17 MOVL DX, edx+20(FP)
18 RET
19
20// func xgetbv() (eax, edx uint32)
21TEXT ·xgetbv(SB),NOSPLIT,$0-8
22 MOVL $0, CX
23 XGETBV
24 MOVL AX, eax+0(FP)
25 MOVL DX, edx+4(FP)
26 RET
diff --git a/vendor/golang.org/x/sys/cpu/cpu_zos.go b/vendor/golang.org/x/sys/cpu/cpu_zos.go
new file mode 100644
index 0000000..5f54683
--- /dev/null
+++ b/vendor/golang.org/x/sys/cpu/cpu_zos.go
@@ -0,0 +1,10 @@
1// Copyright 2020 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5package cpu
6
7func archInit() {
8 doinit()
9 Initialized = true
10}
diff --git a/vendor/golang.org/x/sys/cpu/cpu_zos_s390x.go b/vendor/golang.org/x/sys/cpu/cpu_zos_s390x.go
new file mode 100644
index 0000000..ccb1b70
--- /dev/null
+++ b/vendor/golang.org/x/sys/cpu/cpu_zos_s390x.go
@@ -0,0 +1,25 @@
1// Copyright 2020 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5package cpu
6
7func initS390Xbase() {
8 // get the facilities list
9 facilities := stfle()
10
11 // mandatory
12 S390X.HasZARCH = facilities.Has(zarch)
13 S390X.HasSTFLE = facilities.Has(stflef)
14 S390X.HasLDISP = facilities.Has(ldisp)
15 S390X.HasEIMM = facilities.Has(eimm)
16
17 // optional
18 S390X.HasETF3EH = facilities.Has(etf3eh)
19 S390X.HasDFP = facilities.Has(dfp)
20 S390X.HasMSA = facilities.Has(msa)
21 S390X.HasVX = facilities.Has(vx)
22 if S390X.HasVX {
23 S390X.HasVXE = facilities.Has(vxe)
24 }
25}
diff --git a/vendor/golang.org/x/sys/cpu/endian_big.go b/vendor/golang.org/x/sys/cpu/endian_big.go
new file mode 100644
index 0000000..7fe04b0
--- /dev/null
+++ b/vendor/golang.org/x/sys/cpu/endian_big.go
@@ -0,0 +1,10 @@
1// Copyright 2023 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5//go:build armbe || arm64be || m68k || mips || mips64 || mips64p32 || ppc || ppc64 || s390 || s390x || shbe || sparc || sparc64
6
7package cpu
8
9// IsBigEndian records whether the GOARCH's byte order is big endian.
10const IsBigEndian = true
diff --git a/vendor/golang.org/x/sys/cpu/endian_little.go b/vendor/golang.org/x/sys/cpu/endian_little.go
new file mode 100644
index 0000000..48eccc4
--- /dev/null
+++ b/vendor/golang.org/x/sys/cpu/endian_little.go
@@ -0,0 +1,10 @@
1// Copyright 2023 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5//go:build 386 || amd64 || amd64p32 || alpha || arm || arm64 || loong64 || mipsle || mips64le || mips64p32le || nios2 || ppc64le || riscv || riscv64 || sh || wasm
6
7package cpu
8
9// IsBigEndian records whether the GOARCH's byte order is big endian.
10const IsBigEndian = false
diff --git a/vendor/golang.org/x/sys/cpu/hwcap_linux.go b/vendor/golang.org/x/sys/cpu/hwcap_linux.go
new file mode 100644
index 0000000..34e49f9
--- /dev/null
+++ b/vendor/golang.org/x/sys/cpu/hwcap_linux.go
@@ -0,0 +1,71 @@
1// Copyright 2019 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5package cpu
6
7import (
8 "os"
9)
10
11const (
12 _AT_HWCAP = 16
13 _AT_HWCAP2 = 26
14
15 procAuxv = "/proc/self/auxv"
16
17 uintSize = int(32 << (^uint(0) >> 63))
18)
19
20// For those platforms don't have a 'cpuid' equivalent we use HWCAP/HWCAP2
21// These are initialized in cpu_$GOARCH.go
22// and should not be changed after they are initialized.
23var hwCap uint
24var hwCap2 uint
25
26func readHWCAP() error {
27 // For Go 1.21+, get auxv from the Go runtime.
28 if a := getAuxv(); len(a) > 0 {
29 for len(a) >= 2 {
30 tag, val := a[0], uint(a[1])
31 a = a[2:]
32 switch tag {
33 case _AT_HWCAP:
34 hwCap = val
35 case _AT_HWCAP2:
36 hwCap2 = val
37 }
38 }
39 return nil
40 }
41
42 buf, err := os.ReadFile(procAuxv)
43 if err != nil {
44 // e.g. on android /proc/self/auxv is not accessible, so silently
45 // ignore the error and leave Initialized = false. On some
46 // architectures (e.g. arm64) doinit() implements a fallback
47 // readout and will set Initialized = true again.
48 return err
49 }
50 bo := hostByteOrder()
51 for len(buf) >= 2*(uintSize/8) {
52 var tag, val uint
53 switch uintSize {
54 case 32:
55 tag = uint(bo.Uint32(buf[0:]))
56 val = uint(bo.Uint32(buf[4:]))
57 buf = buf[8:]
58 case 64:
59 tag = uint(bo.Uint64(buf[0:]))
60 val = uint(bo.Uint64(buf[8:]))
61 buf = buf[16:]
62 }
63 switch tag {
64 case _AT_HWCAP:
65 hwCap = val
66 case _AT_HWCAP2:
67 hwCap2 = val
68 }
69 }
70 return nil
71}
diff --git a/vendor/golang.org/x/sys/cpu/parse.go b/vendor/golang.org/x/sys/cpu/parse.go
new file mode 100644
index 0000000..762b63d
--- /dev/null
+++ b/vendor/golang.org/x/sys/cpu/parse.go
@@ -0,0 +1,43 @@
1// Copyright 2022 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5package cpu
6
7import "strconv"
8
9// parseRelease parses a dot-separated version number. It follows the semver
10// syntax, but allows the minor and patch versions to be elided.
11//
12// This is a copy of the Go runtime's parseRelease from
13// https://golang.org/cl/209597.
14func parseRelease(rel string) (major, minor, patch int, ok bool) {
15 // Strip anything after a dash or plus.
16 for i := 0; i < len(rel); i++ {
17 if rel[i] == '-' || rel[i] == '+' {
18 rel = rel[:i]
19 break
20 }
21 }
22
23 next := func() (int, bool) {
24 for i := 0; i < len(rel); i++ {
25 if rel[i] == '.' {
26 ver, err := strconv.Atoi(rel[:i])
27 rel = rel[i+1:]
28 return ver, err == nil
29 }
30 }
31 ver, err := strconv.Atoi(rel)
32 rel = ""
33 return ver, err == nil
34 }
35 if major, ok = next(); !ok || rel == "" {
36 return
37 }
38 if minor, ok = next(); !ok || rel == "" {
39 return
40 }
41 patch, ok = next()
42 return
43}
diff --git a/vendor/golang.org/x/sys/cpu/proc_cpuinfo_linux.go b/vendor/golang.org/x/sys/cpu/proc_cpuinfo_linux.go
new file mode 100644
index 0000000..4cd64c7
--- /dev/null
+++ b/vendor/golang.org/x/sys/cpu/proc_cpuinfo_linux.go
@@ -0,0 +1,53 @@
1// Copyright 2022 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5//go:build linux && arm64
6
7package cpu
8
9import (
10 "errors"
11 "io"
12 "os"
13 "strings"
14)
15
16func readLinuxProcCPUInfo() error {
17 f, err := os.Open("/proc/cpuinfo")
18 if err != nil {
19 return err
20 }
21 defer f.Close()
22
23 var buf [1 << 10]byte // enough for first CPU
24 n, err := io.ReadFull(f, buf[:])
25 if err != nil && err != io.ErrUnexpectedEOF {
26 return err
27 }
28 in := string(buf[:n])
29 const features = "\nFeatures : "
30 i := strings.Index(in, features)
31 if i == -1 {
32 return errors.New("no CPU features found")
33 }
34 in = in[i+len(features):]
35 if i := strings.Index(in, "\n"); i != -1 {
36 in = in[:i]
37 }
38 m := map[string]*bool{}
39
40 initOptions() // need it early here; it's harmless to call twice
41 for _, o := range options {
42 m[o.Name] = o.Feature
43 }
44 // The EVTSTRM field has alias "evstrm" in Go, but Linux calls it "evtstrm".
45 m["evtstrm"] = &ARM64.HasEVTSTRM
46
47 for _, f := range strings.Fields(in) {
48 if p, ok := m[f]; ok {
49 *p = true
50 }
51 }
52 return nil
53}
diff --git a/vendor/golang.org/x/sys/cpu/runtime_auxv.go b/vendor/golang.org/x/sys/cpu/runtime_auxv.go
new file mode 100644
index 0000000..5f92ac9
--- /dev/null
+++ b/vendor/golang.org/x/sys/cpu/runtime_auxv.go
@@ -0,0 +1,16 @@
1// Copyright 2023 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5package cpu
6
7// getAuxvFn is non-nil on Go 1.21+ (via runtime_auxv_go121.go init)
8// on platforms that use auxv.
9var getAuxvFn func() []uintptr
10
11func getAuxv() []uintptr {
12 if getAuxvFn == nil {
13 return nil
14 }
15 return getAuxvFn()
16}
diff --git a/vendor/golang.org/x/sys/cpu/runtime_auxv_go121.go b/vendor/golang.org/x/sys/cpu/runtime_auxv_go121.go
new file mode 100644
index 0000000..4c9788e
--- /dev/null
+++ b/vendor/golang.org/x/sys/cpu/runtime_auxv_go121.go
@@ -0,0 +1,18 @@
1// Copyright 2023 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5//go:build go1.21
6
7package cpu
8
9import (
10 _ "unsafe" // for linkname
11)
12
13//go:linkname runtime_getAuxv runtime.getAuxv
14func runtime_getAuxv() []uintptr
15
16func init() {
17 getAuxvFn = runtime_getAuxv
18}
diff --git a/vendor/golang.org/x/sys/cpu/syscall_aix_gccgo.go b/vendor/golang.org/x/sys/cpu/syscall_aix_gccgo.go
new file mode 100644
index 0000000..1b9ccb0
--- /dev/null
+++ b/vendor/golang.org/x/sys/cpu/syscall_aix_gccgo.go
@@ -0,0 +1,26 @@
1// Copyright 2020 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5// Recreate a getsystemcfg syscall handler instead of
6// using the one provided by x/sys/unix to avoid having
7// the dependency between them. (See golang.org/issue/32102)
8// Moreover, this file will be used during the building of
9// gccgo's libgo and thus must not used a CGo method.
10
11//go:build aix && gccgo
12
13package cpu
14
15import (
16 "syscall"
17)
18
19//extern getsystemcfg
20func gccgoGetsystemcfg(label uint32) (r uint64)
21
22func callgetsystemcfg(label int) (r1 uintptr, e1 syscall.Errno) {
23 r1 = uintptr(gccgoGetsystemcfg(uint32(label)))
24 e1 = syscall.GetErrno()
25 return
26}
diff --git a/vendor/golang.org/x/sys/cpu/syscall_aix_ppc64_gc.go b/vendor/golang.org/x/sys/cpu/syscall_aix_ppc64_gc.go
new file mode 100644
index 0000000..e8b6cdb
--- /dev/null
+++ b/vendor/golang.org/x/sys/cpu/syscall_aix_ppc64_gc.go
@@ -0,0 +1,35 @@
1// Copyright 2019 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5// Minimal copy of x/sys/unix so the cpu package can make a
6// system call on AIX without depending on x/sys/unix.
7// (See golang.org/issue/32102)
8
9//go:build aix && ppc64 && gc
10
11package cpu
12
13import (
14 "syscall"
15 "unsafe"
16)
17
18//go:cgo_import_dynamic libc_getsystemcfg getsystemcfg "libc.a/shr_64.o"
19
20//go:linkname libc_getsystemcfg libc_getsystemcfg
21
22type syscallFunc uintptr
23
24var libc_getsystemcfg syscallFunc
25
26type errno = syscall.Errno
27
28// Implemented in runtime/syscall_aix.go.
29func rawSyscall6(trap, nargs, a1, a2, a3, a4, a5, a6 uintptr) (r1, r2 uintptr, err errno)
30func syscall6(trap, nargs, a1, a2, a3, a4, a5, a6 uintptr) (r1, r2 uintptr, err errno)
31
32func callgetsystemcfg(label int) (r1 uintptr, e1 errno) {
33 r1, _, e1 = syscall6(uintptr(unsafe.Pointer(&libc_getsystemcfg)), 1, uintptr(label), 0, 0, 0, 0, 0)
34 return
35}
generated by cgit v1.2.3 (git 2.45.2) at 2024-12-25 19:49:47 +0000